Fault-Tolerant Systolic Array Design With Partially- Reconfigurable FPGAs

Partial dynamic reconfiguration, PDR, is an important feature of modern reconfigurable architectures such as the Xilinx Virtex FPGA devices. In this paper we focus on the application of PDR to fault-tolerant systolic arrays in one dimension. Single as well as multiple faults in one or more array processing elements, PEs, are considered. In our approach modular redundancy is not used and the goal is to maintain total processing latency of the array at the original non-faulty value. This avoids stalling the data input due to reconfigurations of one set of PEs to another set to work around the fault. We consider arrays of N PEs with all possible single-fault locations and formulate an integer linear programming, ILP, model and constraints for each case. The optimal solution selects the PE to reconfigure as a temporary replacement of the faulty PE, so that total processing latency is not increased when the processing clock rate is higher than the data arrival rate. We also develop a heuristic method for solving the ILP problem, which overlaps as many reconfiguration and data processing tasks as possible. The runtime of the heuristic method is very reasonable and matches the exact ILP solution in each case. Experimental results for a single-fault N PE array show that our heuristic finds optimal temporary reconfigurations so that input data does not have to stall.